In general, assuming that picture data is stored in a memory and encoded, decoded, or anyhow, processed using a microprocessor, a data transfer rate demanded for data transfer between the microprocessor and memory exceeds 100 Mbps. When the picture data is transferred from the microprocessor to the memory over a system bus, the system bus is occupied with the data transfer. This poses a problem in that the processor cannot fulfill its essential signal processing feature. In efforts to solve this problem, an image processing unit has been proposed (Japanese Unexamined Patent Publication Nos. 62-192866, 60-191374, and 7-175759). The image processing unit includes a local memory in which video data or the like is stored, and a local memory bus over which video data is transferred to the local memory independently of the system bus. A microprocessor (CPU) manages bus use authorities given to devices for use of the local memory bus.
The local memory in which video data or the like is stored is accessed directly by an input-output circuit that receives or transmits video, whereby a signal processing time required by the processor can be reduced. Moreover, assuming that image data processing consists of arithmetic operations and signal processing jobs other than the arithmetic operations, the arithmetic operations should be processed using an arithmetic unit incorporated in the processor, while the other signal processing jobs should be performed as a parallel operation at a high speed. If the signal processing jobs are executed using a dedicated arithmetic circuit, they can be achieved at a higher processing speed. From this viewpoint, the local memory should preferably be designed so that it can be accessed by a circuit that receives or transmits a video signal, a video processing circuit that uses a dedicated arithmetic unit to process a video signal, and a processor alike.